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ATmega128
? Bit 4 – TWSTO: TWI STOP Condition Bit
W riting the T W STO bit to one in Master mode will generate a STOP condition on the Two-wire
Serial Bus. W hen the STOP condition is executed on the bus, the T W STO bit is cleared auto-
matically. In slave mode, setting the T W STO bit can be used to recover from an error condition.
This will not generate a STOP condition, but the T W I returns to a well-defined unaddressed
Slave mode and releases the SCL and SDA lines to a high impedance state.
? Bit 3 – TWWC: TWI Write Collision Flag
The T WW C bit is set when attempting to write to the T W I Data Register – T W DR when T W INT is
low. This flag is cleared by writing the T W DR Register when T W INT is high.
? Bit 2 – TWEN: TWI Enable Bit
The T W EN bit enables T W I operation and activates the T W I interface. W hen T W EN is written to
one, the T W I takes control over the I/O pins connected to the SCL and SDA pins, enabling the
slew-rate limiters and spike filters. If this bit is written to zero, the T W I is switched off and all T W I
transmissions are terminated, regardless of any ongoing operation.
? Bit 1 – Res: Reserved Bit
This bit is a reserved bit and will always read as zero.
? Bit 0 – TWIE: TWI Interrupt Enable
W hen this bit is written to one, and the I-bit in SREG is set, the T W I interrupt request will be acti-
vated for as long as the T W INT flag is high.
TWI Status Register –
TWSR
Bit
Read/ W rite
Initial Value
7
TWS7
R
1
6
TWS6
R
1
5
TWS5
R
1
4
TWS4
R
1
3
TWS3
R
1
2
–
R
0
1
TWPS1
R/ W
0
0
TWPS0
R/ W
0
TWSR
? Bits 7..3 – TWS: TWI Status
These 5 bits reflect the status of the T W I logic and the Two-wire Serial Bus. The different status
codes are described later in this section. Note that the value read from T W SR contains both the
5-bit status value and the 2-bit prescaler value. The application designer should mask the pres-
caler bits to zero when checking the Status bits. This makes status checking independent of
prescaler setting. This approach is used in this datasheet, unless otherwise noted.
? Bit 2 – Res: Reserved Bit
This bit is reserved and will always read as zero.
? Bits 1..0 – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler.
Table 87. T W I Bit Rate Prescaler
TWPS1
0
0
1
1
TWPS0
0
1
0
1
Prescaler Value
1
4
16
64
To calculate bit rates, see “Bit Rate Generator Unit” on page 203 . The value of T W PS1..0 is
used in the equation.
206
2467X–AVR–06/11
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